1. Field
Example embodiments relate to a semiconductor chip, a flip chip package and a wafer level package including the semiconductor chip. More particularly, example embodiments relate to a pad arrangement of a semiconductor chip, a flip chip package and a wafer level package including the semiconductor chip.
2. Description of the Related Art
Generally, a semiconductor chip may include peripheral pads arranged on an edge region of the semiconductor chip, and central pads arranged on a central region of the semiconductor chip. The peripheral pads may include an input pad, an output pad, a test pad, for example. The central pads may include a signal pad.
According to related arts, a peripheral pad may be used only for a test pad of a semiconductor package test or a bonding pad of a conductive wire. A central pad may be used for bonding pads in a flip chip package or a connecting pad of a redistribution layer in a wafer level package. That is, a peripheral pad may not be used for the bonding pad in the flip chip package or the connecting pad of the redistribution layer in the wafer level package. When an interval between the central pads corresponds to a fine pitch between conductive bumps in the flip chip package, an electrical short may occur among the conductive bumps. As a result, in order to prevent the electrical short among the conductive bumps, the flip chip package may have a large size. Particularly, in order to electrically connect the semiconductor chips with a package substrate in a system-in-package (SIP), the package substrate may have a large size.